1. Field of the Invention
The present invention relates to a dielectric structure of a deep trench capacitor for a dynamic random access memory (DRAM) cell and, more particularly, to a SiN/SiON dielectric structure for improving capacitance and reducing leakage current and a method of forming thereof.
2. Description of the Related Art
There is much interest in reducing the size of individual semiconductor devices in order to increase their density on an integrated circuit (IC) chip, thereby reducing size and power consumption of the chip, and allowing faster operation. In order to achieve a memory cell with a minimum size, the gate length in a conventional transistor must be reduced to decrease the lateral dimension of the memory cell. However, the shorter gate length will result in higher leakage currents that cannot be tolerated, and the voltage on the bit line must therefore also be scaled down. This reduces the charges stored on a storage capacitor, and thus requires a larger capacitance to ensure that stored charges are sensed correctly. Recently, in fabricating highly-integrated memory devices, such as dynamic random access memory (DRAM), a deep trench capacitor has been developed within a silicon substrate without consuming any additional wafer area.
In order to prolong the data retention time, the capacitance of the storage capacitor must be increased by increasing the capacitor area, decreasing the effective dielectric thickness between the capacitor plates, or increasing the dielectric constant (k) of the capacitor dielectric. However, increasing the capacitor area conflicts with the need to shrink the memory cell, and reducing the dielectric thickness is difficult because the dielectric thickness has already been reduced to a practical minimum. Therefore, improving the capacitor dielectric with a high dielectric constant is a way to provide adequate capacitance in view of shrinking cell size.
Conventionally, the most prominent material used to from the capacitor dielectric is Ta2O or Al2O3 that facilitates the refining process for making a thinner layer, but fails in high-k dielectric application. Accordingly, various multilayered structures including oxide and nitride, such as SiO2/SiN/SiO2, SiN/SiO2 and SiN/SiO2/SiON, have been developed for forming the capacitor dielectric.
FIG. 1 is a sectional diagram showing a conventional deep trench capacitor. A DRAM cell comprises a transistor 22 and a deep trench capacitor 20 having a bottom electrode plate 14, a capacitor dielectric 16 and an upper electrode plate 18. The bottom electrode plate 14 can be formed from the n+-doped region in a silicon substrate 10 surrounding a deep trench 12 or from a doped-polysilicon layer that conformally covers the sidewall and the bottom of the deep trench 12. The upper electrode plate 18 is formed by filling the deep trench 12 with a conductive layer.
FIG. 2A is a conventional SiO2/SiN/SiO2 dielectric structure served as the capacitor dielectric 16. A multi-layered SiO2/SiN/SiO2 structure, called an ONO structure, has been employed as the capacitor dielectric 16. Because the SiN dielectric constant (k=7.6) is 1.5˜2 times larger than that of the SiO2 dielectric constant (k=3.9), the SiN layer in the ONO structure can increase the capacitance of the deep trench capacitor. The SiO2 layer in the ONO structure is employed to repair the damaged interface. Nevertheless, the critical thickness of the ONO structure has a limitation of 5-10 nm, the dielectric constant of the ONO structure only reaches approximately 7, and problems of difficult process, low yield, high process cost, and leakage current occur.
FIG. 2B is a conventional SiN/SiO2 dielectric structure served as the capacitor dielectric 16. A stacked SiN/SiO2 structure, called a NO structure, has been employed to form the capacitor dielectric 16. The NO structure comprises a SiN liner deposited on the sidewall and bottom of the deep trench 12 by low pressure vapor deposition (LPCVD) and a thin SiO2 layer grown on the SiN liner by re-oxidation process. In the NO structure, the SiN liner with a dielectric constant 1.5˜2 times larger than the dielectric constant of the thin SiO2 layer, the thickness of the SiN liner is 40˜80 Å and the thickness of the SiO2 layer is 3 nm. Thus, the capacitance of the deep trench capacitor is effectively increased. However, there is still a problem of leakage current caused by the SiN liner. Also, during deposition of the SiN liner, the process gases, such as SiH4 and NH3, cause pinhole structure defects in the SiN liner. Although the SiO2 layer grown on the SiN liner can repair the defects, decrease the pinhole density and reduce leakage current to achieve a preferred distribution of breakdown voltage, the SiN liner is too thin to increase the dielectric constant of the NO structure.
FIG. 2C is a conventional SiN/SiO2/SiON dielectric structure served as the capacitor dielectric 16. A stacked SiN/SiO2/SiON structure has been employed to form the capacitor dielectric 16, in which a post oxidation annealing with NH3 is employed on the above-described NO structure to form a SiON layer on the SiO2 layer. The SiON layer contributes a higher dielectric constant to the capacitor dielectric 16, resulting in a significantly improved capacitance. However, the stacked SiN/SiO2/SiON structure suffers from remarkably leakage current due to the usage of hydrogen-containing gas, such as NH3, in the formation of the SiON layer.